Intel unveiled Xeon 6+, codenamed Clearwater Forest, at Computex: its first data-centre CPU built on the Intel 18A process, scaling to 288 efficiency cores per socket.
The specs
The chip uses a tiled design, with compute tiles on 18A joined to base and I/O tiles through EMIB and Foveros Direct packaging. Memory runs 12 channels of DDR5 at up to 8 GT/s with MRDIMM support, I/O reaches 96 lanes of PCIe 5.0 plus 64 lanes of CXL, and TDP scales to 450W. Intel cites roughly 17% higher instructions-per-clock than the prior E-core generation.
What 288 E-cores means for security infrastructure
E-core-heavy parts are not about single-thread speed; they are about how many independent things one socket can do at once. A video estate is exactly that workload: hundreds of camera streams, each needing ingest, motion evaluation, indexing, and health monitoring, none of it demanding on its own but relentless in aggregate. The same logic covers multi-tenant VMS hosting and the CPU side of analytics pipelines, where pre-processing and metadata handling queue up around the GPUs.
The practical consequence is rack math. Where a recording tier once meant a row of mid-range dual-socket servers, a single-socket, high-density box can absorb several of them, cutting power and licence counts along the way.
The read
Between this and the high-core AMD parts landing this year, the per-server capacity assumption baked into most VMS sizing guides is now stale. Resize before quoting hardware refreshes, not after.